1. Field of the Invention
The present invention relates to package structures, and, more particularly, to a package structure with embedded electronic components and a method of fabricating the same.
2. Description of Related Art
As the packaging technology advances, semiconductor devices with different types of chip packaging technologies have been developed to be incorporated in various different electronic devices such as smart phones, tablets, networks, or laptops. Such semiconductor device mainly involves disposing a chip on a package substrate, where the chip is electrically connected with the package substrate, followed by an encapsulating process with the use of an encapsulating material. In order to reduce the package height, a type of package with the chip embedded in a package substrate is preferred, as the overall package size is reduced while the electrical performance is improved.
FIGS. 1A-1D are cross-sectional views showing a method of fabricating a package structure according to the conventional art.
As shown in FIG. 1A, a core board 13 having a through opening 130 is provided, and a plurality of inner wirings 11 and a copper window 110 are formed on top and bottom sides of the core board 13. A plurality of conductive pillars 12 are formed in the core board 13 for electrically connecting the inner wirings 11 on the top and bottom sides of the core board 13.
As shown in FIG. 1B, a carrier board 10 such as a polyimide (PI) tape is disposed on the bottom side of the core board 13, so as to receive a semiconductor chip 18 having a plurality of electrode pads 180 in the opening 130, as well as disposing the semiconductor chip 18 on the carrier board 10. With the design of the copper window 110, the semiconductor chip 18 is prevented from contacting the inner wirings 11.
As shown in FIG. 1C, a dielectric material is laminated on the top side of the core board 13 and on the semiconductor chip 18, so as to fill in gaps between walls of the opening 130 and semiconductor chip 18. Then, the carrier board 10 is removed, and another dielectric material is laminated on the bottom side of the core board 13, such that the two dielectric materials form a dielectric layer 16.
As shown in FIG. 1D, wiring layers 14 are formed on the top and bottom sides of the dielectric layer 16, respectively, and the wiring layer 14 has conductors 15 formed in the dielectric layer 16 and electrically connected with the electrode pads 180 and the inner wirings 11.
However, in the method of fabricating a package structure 1 according to the conventional art, the copper window 110 is used to serve as a spacing layer, which undesirably diminishes the routable regions for the inner wirings 11. Moreover, an additional laser process with the use of CO2 laser to form the opening 130 increases the cost, and the organic glass fibers of core board 13 are exposed, which would result in poor yield and poor quality of the placement of the semiconductor chip 18.
Further, a laser process is required to form blind holes (i.e. at the corresponding positions of the conductors 15) or vias (i.e. at the corresponding positions of the conductive pillars 12), such that the shapes of the holes or vias can only be circular and not as desired.
In addition, with the use of PI tape as the carrier board 10 to fix the semiconductor chip 18 is also undesirable, which not only requires additional processes for attaching and detaching the tapes, additional cost involved for the tapes and other equipment is also undesirable.
Moreover, it is required to fabricate the dielectric material twice, followed by a laminating process, to form the dielectric layer 16. As such, a pre-pressing and a curing pressing process are required, which not only is time consuming and expensive, it may also lead to dislocation (or even spinning) of the semiconductor chip 18, such that an accurate alignment for positioning the semiconductor chip 18 in the opening 130 is not easy, resulting in a poor alignment between the electrode pads 180 of the semiconductor chip 18 and the conductors 15. Accordingly, poor electrical connection or electrical connection failure may occur and lead to a poor yield.
FIGS. 1A′-1D′ show another method of fabricating package structure according to the conventional art.
As shown in FIG. 1A′, a first wiring layer 11′ is formed on a carrier board 10 such as a copper foil substrate, and a passive component 18′ such as a multi-layered ceramic capacitor (MLCC) is securely fixed on the first wiring layer 11′ by an insulating adhesive 180′.
As shown in FIG. 1B′, a first dielectric material layer 13′ having an opening 130 for fixing the passive component 18′ therein is formed on the carrier board 10.
As shown in FIG. 1C′, a second dielectric material layer is formed and laminated on the top side of the first dielectric material layer 13′ and on the passive component 18′, and the second dielectric material layer is filled in gaps between walls of the opening 130 and the passive component 18′, allowing the first dielectric material layer 13′ and the second dielectric material layer to be heat-pressed to form a dielectric encapsulating layer 16′, so as to securely fix the passive component 18′ and the first wiring layer 11′ in the dielectric encapsulating layer 16′.
As shown in FIG. 1D′, a second wiring layer 14′ is formed on the top side of the dielectric encapsulating layer 16′, and the second wiring layer 14′ has conductors 15 formed in the dielectric encapsulating layer 16′ and electrically connected with the passive component 18′. After that, the carrier board 10 is removed to expose the first wiring layer 11′.
However, according to the conventional method of fabricating the package structure 1′, since the copper coil substrate is used to serve as the carrier board 10, delaminating may easily occur resulting in structural damages. Also, a laser process is employed to make blind holes (i.e., at the corresponding positions of the conductors 15), such that only circular shaped openings could be made and the shapes of the openings are undesirable.
Further, as non-conductive material and dispensing method are used to attach the passive component 18′, and the diameter of the dispensed particle is more than 200 μm, the dispensed adhesive in each dispensing process varies greatly in size of the diameter and is difficult to be controlled, causing the adhesive 180′ to easily spread to other regions, thus contaminating the wirings of the first wiring layer 11′ thereby resulting in poor reliability.
Moreover, it is required to fabricate the dielectric material twice, followed by a laminating process to form the dielectric layer 16′. As such, the first dielectric layer 13′ and the second dielectric layer can easily be dislocated, thereby increasing the fabricating time and cost. Moreover, after placing the passive component 18′ and before curing the dielectric encapsulating layer 16′, the passive component 18′ is not fixed yet, and can easily dislocate, resulting in a poor yield.
In addition, with the use of the conductors 15 to establish an electrical connection path to one side of the passive component 18′, the electrical path is increased as well as the risk of signal loss is raised, and thus the cost of using unconventional MLCC as the passive component 18′ is significantly high.
Accordingly, there is an urgent need for solving the foregoing problems of the conventional arts.